Also, you’ll notice that Google Ads are prominently displayed on this blog. I wanted to recoup the hosting costs of running this blog. Unfortunately, that didn’t end up being as profitable as I thought. So, as soon as I hit $100 of ad revenue (which is the minimum to cash out of my Google AdSense account), I’ll remove the ads. I’ll essentially be eating the hosting cost (in addition to the time I’ve put into the blog).

Unless I change my mind. Which is unlikely.

Also, I might try out some more social features on the web site. If I get the time. Which is also unlikely.

Unfortunately, this can’t be done over a large range, because as Foster’s reactance theorem states, as soon as you deviate a little from your center frequency, both the inductive reactance of your antenna and the reactance of whatever you’re using to cancel it (most likely a capacitive element) both increase (go toward ). So, for every change in frequency from the center frequency, your antenna reactance goes up by some amount , but your matching element’s reactance also goes up by some amount .

If you had a Non-Foster element, the reactance of your tuning element would go down by some amount , compensating for the increased reactance of the antenna. You would then have  a broadband (or broader) match.

Most attempts to do this have required the use of active elements (such as gyrators) so synthesis a negative impedance. However, I’m wondering if  a switched-capacitor circuit can be used to synthesize this Non-Foster reactance. Most analyses of switched-capacitor circuits show that they are synthetic resistors at frequencies far below the switching frequency. However, what does the impedance look like near the switching frequency?

Well, since you’re pumping current into the circuit at exactly the rate of switching, you should see a large voltage. As a result, it should look like a high-impedance near the switching frequency. I would tend to believe that the switching function takes the usual function and modulates it up to the switching frequency. (I haven’t proved this and probably won’t ever prove it.) However, if one thinks about the following picture, the current coming into the capacitor can be seen as the independent variable. Then, the voltage is the regular voltage, except mixed by the switching function. Thus, the product should be some modulated version of the fundamental capacitor’s impedance.

The upshot of all this mixing is that just below the switching frequency, one would have a reactance that’s decreasing. (I’m doing a considerable amount of hand-waiving here, excluding such things as aliases of the switching harmonics.) What’s even cooler about this reactance is that the Non-Foster region is determined by the switching frequency–so, one could move it around just by changing the switching frequency. You’d effectively have a digitally-tunable antenna.

There are a number of problems with this scheme, most notably the radiation of switching noise and any switched-capacitor noise effects. However, I think it’s worth looking at and building upon.

If the distribution is Gaussian, the mean and median are equal.

(Mean is defined as where is the probability distribution function (PDF) of —that is, it’s a average of X, weighted with the probability density of . The median defined as —that is, the point where is equally likely to be lower than or greater than (50% probability).)

Many times in engineering and process control, we keep track of the mean and standard deviation. One of the reasons is that if the thing we’re trying to control is Gaussian, the mean/median and standard deviation give us good design criteria to minimize failure: if we allow our system to tolerate 3 standard deviations () around the mean/median, then it has a 99.7% chance of success (0.3% chance of failure).

However, we can generalize this: if we wanted to be more lax, we could only design (or require) the system to tolerate 2 standard deviations (4.5% failure). In some cases, systems are designed to tolerate 4 standard deviations (0.006% failure). So, one can design the system to tolerate , where is some factor (3, 2, 4 for example) that determines the probability of failure.

However, what if the distribution is bimodal? Take for example, two modes of operation (each more or less Gaussian):

Due to the asymmetric distribution, the mean and median are now not the same. In this case, we could posit that some secondary mode (or external factor) causes that second hump. Let’s call the main hump the primary mode and the smaller hump the secondary mode. If things are behaving “normally” we get the first hump, but some failure or aberration causes the second hump.

However, what if the system was more sensitive to this failure (secondary mode). Then, we’d see something like:

Notice what happened? The median stayed exactly the same. However the mean mislabeled “average”) moved proportionally to that secondary hump. Incidentally, the standard deviation () also moved proportionally to the distance between the two humps—but let’s focus on the fact that the mean just changed.

The question you’re probably asking is “what’s so bad about that”? Well, if you’re computing six-sigma-like design criteria, you’re taking . Recall, however, that we could pick any factor depending on the probability of failure we want (I should say want to avoid). So, when both the average and the standard deviation change, how can we be sure we’re getting the right value for ?

The nice thing about picking the median as the average is that it doesn’t depend on the magnitude of the secondary mode—only on the probability of the secondary mode. The magnitude of failure impacts the standard deviation. I like to view these (median and standard deviation) sas two independent metrics that tell different stories.

Another thing to note is that one could view the 2nd illustration above as an input to a nonlinear amplifier (for example) and the 3rd illustration as the output. That’s another nice thing about the median: it commutes with a monotonic nonlinearity. That is, if is monotonic, and , then . So, we don’t have to worry so much that we’re measuring the correct independent variable. Our median will give us the same information (albeit in a different, nonlinear domain).

Expect a bit more down-time: I’m going to do a bit of experimentation to ensure that future down-time doesn’t happen again (improve reliability).

You rock, Justin! I (and my readers) thank you.

You’ll notice that this post has Matt Miller listed as the author. Poojan requested Matt’s comments on his differential circuit post. Poojan was impressed with my comments enough that he decided to make it a follow-up post. So, this post is co-written by both Poojan and Matt.

Gain

Some of you asked whether the differential circuit being biased at half the current therefore has half the transconductance, and therefore lower gain. The answer is that it depends.
The single-ended circuit has an output current $$i_o = g_m \times v_i$$. In many cases, the only thing this circuit can drive is a single-ended load $$Z_L$$.
The differential circuit has an output current $$i_{o+} = g_m \times v_i/2$$; $$i_{o-} = -g_m \times v_i/2$$.
So, the question comes down to whether we can subtract the two currents $$i_{o+}$$ and $$i_{o-}$$ to produce a differential current. Although one can think of it that way, it’s really more accurately to define the current flowing out of one side and into the other. The current, therefore, doesn’t change. However, all other things being equal, the load on the differential circuit will be $$2Z_L$$. Therefore, the gain is the same.

Free Lunch

Some of you questioned the 4x boost in dynamic range that the differential circuit gives over its single-ended counterpart. While I made some mistakes with the equations (they’re fixed now), the result was correct: the differential circuit does have 6 dB higher dynamic range. Where did this come from? Well, it’s the basic advantage of the differential circuit: while a single-ended circuit can only swing +/- Vx, a differential circuit (where the output is defined as the difference of two single-ended circuits) has a swing of twice that: +/- 2Vx. Having twice the voltage is equivalent to 4x the power (and in both cases, that’s 6 dB improvement).

There’s No Such Thing

If some of you feel that this can’t be possible, please keep in mind the long disclaimer at the beginning of the last post: there are no universally better circuits. There are only certain circuits that are better suited for certain applications. In this case, the differential circuit gets its benefit from improved output range. However, the gain doesn’t change. Therefore, there’s an intrinsic assumption here: the circuit will tolerate a higher output, but there’s no gain to make the output higher. We didn’t intrinsically get double the gain, so we can’t take advantage of the dynamic range without sticking some gain ahead of the circuit.
That’s requirement is perfectly fine in a lot of cases. In many cases, you already have a ton of gain and automatic gain-control (AGC) ahead of the circuit. In that case, the AGC range can be reduced (possibly improving overall performance). This is true (for example) in the baseband filter at the end of an RF line-up. For that application, the figure of merit really is dynamic range. Similarly, in an ADC, the extra dynamic range might mean more effective bits of resolution.

Cheap Lunch

We’ve given the impression that the dynamic range can’t be leveraged in (for example) an RF LNA. Turns out that it can—for relatively cheap (although  not for free). If one were to stick a 1:4 (impedance ratio) balun ahead of the circuit, one would get this voltage gain for relatively cheap (meaning, the cost of the balun). In many cases, some form of impedance transformer (matching network) is required anyway, so putting a balun in isn’t a great cost.
The balun doubles the voltage but quadruples the output impedance. This is actually a good thing: the differential circuit has 4x the input impedance of the single-ended circuit. Let’s call the single-ended circuit’s input impedance $$Z_i$$. The differential circuit has $$2Z_i$$ input impedance on each side (we’ve cut the single-ended circuit in half). However, these input impedances get stacked to form the fully differential input impedance, so we get $$4Z_i$$ as the input impedance of the differential circuit:

versus

From my personal blog:

I’ve been lucky enough to find myself in a team that’s intent on finding the best circuit design for a given application. This doesn’t happen often to many people, but I feel that I’ve had more than my share of this opportunity.

The conclusion is usually that we come up with some topology (let’s call it circuit X) that optimizes all the performance criteria. I walk away wanting to generalize the experience with the lesson that circuit X is the best circuit ever, and I want to use it everywhere.

Inevitably, I find that some other topology Y is better suited for some other application. There were some specific constraints or conditions on circuit X that don’t apply to circuit Y, and as a result, circuit Y is more optimal for application Y.

It is for this reason that I won’t say that differential circuits are always better than their single ended counter-part. I will say that in my experience, I’ve come across the case where the differential circuit—or, really, the differential approach—is more effective than its single-ended counterpart. However, that’s not why I’ve decided to write this post.

Unfortunately, I’ve come across several engineers that make the generalization error in the opposite direction: they state that single-ended circuits save current. I will present a counter-example that is sufficient to disprove this generalization. Keep in mind that it doesn’t prove the opposite generalization (that differential circuits are always better).

Voltage-Mode Output

The two cases below assume that the dynamic range is limited by output voltage: that is, the circuit will clip its output and that determines the high-end of the dynamic range.

Single-Ended Dynamic Range

Consider the single-ended CMOS amplifier shown below:

The output noise voltage is given by:

$$v_{n,o}^2 = \frac{8kTg_m \times |Z_L|^2}{3} = \frac{8kT \times I_{DD} \times |Z_L|^2}{3*V_{DSAT,N}}$$

The maximum output voltage swing (zero-to-peak) is given by:

$$V_{o,max} = \frac{V_{DD} – V_{DSAT,P} – V_{DSAT,N}}{2}$$

The dynamic range is:

$$DR = \frac{|V_{o,max}|^2}{v_{n,o}^2} = \frac{(V_{DD} – V_{DSAT,P} – V_{DSAT,N})^2 \times 3V_{DSAT,N}}{4 \times 8kT \times I_{DD} \times |Z_L|^2}$$

Differential Dynamic Range

Consider the differential CMOS amplifier:

The output noise voltage is given by (I_D is the current in each side of the differential pair; it is half of I_DD, the total current):

$$v_{n,o}^2 = \frac{8kTg_m \times |Z_L|^2}{3} = \frac{8kT \times 2 \times I_{D} \times |Z_L|^2}{3*V_{DSAT,N}} = \frac{8kT \times I_{DD} \times |Z_L|^2}{3*V_{DSAT,N}}$$

The maximum output voltage swing (zero-to-peak) is given by:

$$V_{o,max} = V_{DD} – V_{DSAT,P} – V_{DSAT,N} – V_{DSAT,N2}$$

The dynamic range is:

$$DR = \frac{|V_{o,max}|^2}{v_{n,o}^2} = \frac{4(V_{DD} – V_{DSAT,P} – V_{DSAT,N} – V_{DSAT,N2})^2 \times 3V_{DSAT,N}}{4 \times 8kT \times I_{DD} \times |Z_L|^2}$$

Comparison

We see that the dynamic range is equivalent in both cases. The difference is the terms 4(V_DD – V_DSAT,P – V_DSAT,N – V_DSAT,N2) in the differential case versus (V_DD – V_DSAT,P – V_DSAT,N) in the single-ended case. In many cases, the differential dynamic range is larger. In fact, as long as

V_DSAT,N2 < 3/4(V_DD – V_DSAT,P – V_DSAT,N)

However, in the case where you can’t meet this requirement, you can get rid of MN2 (albeit at the cost of common-mode rejection).

Conclusion

We’ve seen a case where the differential circuit shows more dynamic range than the single-ended counterpart. My guess is that most people who say that differential means more current don’t realize that you don’t have to have the same current in each branch of the differential circuit (you can split the current in half).

One limitation of the above analysis is that I assume that the input voltage is available in a differential form, and that the output is consumable in its differential form. Obviously, if this isn’t the case, the above analysis may or may not work. The case becomes more specific and the generalization fails.

That said, I’ve seen plenty of line-ups where a transformer/balun is placed off-chip to convert the chip’s inputs/outputs to differential. Requiring differential I/O at the chip level doesn’t mean requiring differential I/O at the board level.

Current-Mode Output

I’ve detailed the use of current-mode circuits before. It’s possible to treat this as a special case of the voltage-mode output analysis, with Z_L being small. The only problem with that extrapolation is that if Z_L is small, the maximum swing probably won’t be dictated by voltage: the circuit will slew way before it clips. As a result, instead of V_o,max being given by the previous equation, we have:

Single-ended:

$$V_{o,max} = \frac{\alpha \times I_{DD} \times |Z_L|}{2}$$

Differential:

$$V_{o,max} = \alpha \times I_{DD} \times |Z_L|$$

where α is a factor that indicates what fraction of quiescent current can be used as signal current.

The advantage is even more apparent: you’re getting 4× the dynamic range.

Additional Benefits

In addition to the improved dynamic range (power-drain efficiency), differential circuits offer:

• Reduced susceptibility to supply noise: a good chunk of supply noise appears as common-mode, so a fully-differential circuit will reject (ignore) it
• Improved IM2: IM2 generally appears as common-mode and to a large amount gets rejected
• Reduce supply bounce (more beneficial for switch-mode circuits): since there’s a complementary action at the nodes in the differential circuit, much less noise is induced on the supply during dynamic operation

Disadvantages

I can only point out a few disadvantages to the approaches presented here—and they really have nothing to do with single-ended (versus differential) circuits:

• Common-mode feedback: you’re generally going to need a common-mode feedback (and common-mode sensing). However, even the single-ended topology (shown above) requires some bias adjustment to set its output bias voltage. This is more of a property of CMOS design (high-impedance loads) than a trade-off of single-ended/differential circuits.
• Lower swing: once again, this is a property of the differential pair. But, a lot of the differential benefit (common-mode rejection ratio) comes from using the differential pair.

True disadvantages:

• If you’re using minimum-size devices, you end up spending twice the current with the differential circuit than with the single-ended version. However, when (in analog design), have you used minimum-sized devices?
• The benefits of differential circuits occur when you get to analyze the noise and signal swing differentially. However, if the circuit you’re driving doesn’t respond to a differential input, the benefits aren’t as great.

Conclusion

It seems to me that most of the people that globally avoid differential circuits subscribe to the thought that since there are two current branches, there must be double the current. However, like I said above, this is only true if your branches are using minimum-sized devices. Otherwise, you can always split the device in half and distribute the same current across a differential pair.

I know a very good IC designer and PCB designer. My experience with him is as an IC layout designer. However, most of his PCB customers cite him as the best PCB layout designer they’ve come across. I’ll focus on his IC skills, since I can attest to that.

He’s most often hired as a consultant embedded in a design team. However, he’s capable of and set up for turn-key work (taking schematics and sending back GDS II). He’s skilled in Cadence (Virtuoso XL, Assura) and Mentor (IC Layout, Calibre) design tools.

If you’re interested, fill out the Feedback (Contact Us) form. I will forward requests to him.

He’s worked on the following products (since I’ve met him) and much more:

• CMOS 90 nm transceiver IC including ADC/DAC, RF: massive integration effort, requiring careful shielding and differential matching of many RF/analog lines
• IBM 8WL BiCMOS IC including high-linearity mixer with feedback: extremely compact layout, minimizing RF parasitics
• CMOS 90 nm continuous-time sigma-delta ADC: detailed matching (common centroiding) of CMOS devices and matching of routing parasitics
• TSMC 0.18 um CMOS class-D audio amplifier IC: integration and isolation of several analog blocks with large digital circuit
• CMOS 0.18 um all-digital RF transmitter (resulted in this publication)

Each of the above has been a first-pass success. He contracted for over a decade at Motorola Labs (Motorola’s corporate research center at their headquarters near Chicago), Atmel, Freescale Semiconductor, and several Motorola product groups. He ran a circuit board development group at Tellabs. He’s extremely pleasant to work with and does very well in a team environment (both as a lead developer and as a team member).

He is a US citizen.

He is available for hourly contracting.

Introduction

In general, we are trying to produce the signal

where is the in-phase (I) component and is the quadrature (Q) of our complex baseband signal. In general, RF transmitters have a modulator circuit which carries out this math. These are called Cartesian modulators and are generally drawn as:

This diagram is meant to be interpreted as a high-level circuit schematic. Namely, the output is a wire-sum of the the individual mixer outputs.

can also be written as

where and . Then, we lose the need to sum the signals and we can simply implement:

Cartesian Inefficiency

The inefficiency of the Cartesian modulator is not in the individual mixers themselves (they are equivalent between Cartesian and polar). The inefficiency lies in the summing of the two mixer outputs: some current flows from the I-mixer into the Q-mixer and is dissipated by the Q-mixer’s output resistance. Indeed, we could get a high efficiency RF modulator if we could stop this current flowing. Indeed, if the component mixers were high output impedance (i.e. current sources), this summing could be done efficiently.

Switched-Mode Modulators

It should be noted that while we desire , what usually gets implemented is where is a square wave at the carrier frequency. This works because has a component of —albeit with some higher order terms. However, these terms can usually be filtered out.

Interleaving

What if, instead of summing the two signals, we interleaved them. That is, we spit out a sequence (at 4x the carrier frequency) of [+ x_I, –x_Q, –x_I, +x_Q]? It turns out that this is equivalent to multiplying by a [+1,0,-1,0] sequence (which also has a term of ) and multiplying by a [0, –1, 0, +1] sequence (which has a term of ).

It turns out that the cases where the I- and Q- LO’s overlap is very inefficient, and it contributes nothing to the output signal power. (The term in [+1, 0, –1, 0] is smaller than the term in [+1, +1, –1, –1]. However, we are concerned about efficiency—the ratio of power produced to power dissipated—not absolute output power.)

This can be implemented efficiently by the following switching circuit:

For clarity, I’ve shown the circuit as a single-balanced (single-ended) output, but it can be (and should be) implemented as a fully differential output.

So, we want to break down our continuous-time sigma-delta feedback into two paths:

1. A low-precision tight loop that delivers the first sample to the quantizer
2. A higher-precision loop that goes through a clock delay to minimize “metastability” (indecision)

DAC Feedback

As a small aside, recall that the DAC feedback looks similar to the following:

The input to the quantizer is the convolution of this signal with the impulse response h(t) of the noise-shaping filter H(s). As we did with the impulse-invariant transform, we break down the noise-shaping filter into partial-fraction expansion:

Each of these is a single-pole filter, with an impulse response that looks something like:

Dual-Filter Analysis

The first sample at the quantizer is the convolution of a DAC symbol with the impulse response. This amounts to the integral over one sample period:

The rest of the samples can be passed through a filter that looks like this:

The main difference between this remaining filter and the original is that it is scaled by . Note that the delay in the filter is already included in the system due to the extra clock delay by the second DAC.

Summary

So, in the end, we have replaced with: